code: def _get_schedule_rules_for_x86(intrin):
      return [
          ms.schedule_rule.ApplyCustomRule(),
          ms.schedule_rule.AutoInline(
              into_producer=False,
              into_consumer=True,
              inline_const_tensor=True,
              disallow_if_then_else=True,
              require_injective=True,
              require_ordered=True,
              disallow_op=["tir.exp"],
          ),
          ms.schedule_rule.AddRFactor(
              max_jobs_per_core=16, max_innermost_factor=64
          ),
          ms.schedule_rule.MultiLevelTilingWithIntrin(
              intrin,
              structure="SSRSRS",
              tile_binds=None,
              max_innermost_factor=64,
              vector_load_lens=None,
              reuse_read=None,
              reuse_write=ms.schedule_rule.ReuseType(
                  req="may",
                  levels=[1, 2],
                  scope="global",
              ),
          ),
          ms.schedule_rule.MultiLevelTiling(
              structure="SSRSRS",
              tile_binds=None,
              max_innermost_factor=64,
              vector_load_lens=None,
              reuse_read=None,
              reuse_write=ms.schedule_rule.ReuseType(
                  req="may",
                  levels=[1, 2],
                  scope="global",
              ),
          ),
          ms.schedule_rule.ParallelizeVectorizeUnroll(
              max_jobs_per_core=16,
              max_vectorize_extent=64,
              unroll_max_steps=[0, 16, 64, 512],
              unroll_explicit=True,
          ),
          ms.schedule_rule.RandomComputeLocation(),
      ]
  
imports: import tempfile
  import numpy
  import pytest
  import tvm
  import tvm.testing
  import tvm.topi.testing
  from tvm import meta_schedule
  from tvm import relay
  from tvm.meta_schedule.testing import relay_workload
  from tvm.meta_schedule.testing.tlcbench import load_quantized_bert_base
  from tvm.tir.tensor_intrin.arm_cpu import DP4A_INTRIN
  from tvm.tir.tensor_intrin.rocm import AMDGPU_SDOT4_INTRIN
  from tvm.tir.tensor_intrin.x86 import VNNI_DOT_16x4_INTRIN
  from tvm.tir.tensor_intrin.x86 import AVX512_DOT_16x4_INTRIN
label_desc: Use image node_id 1 for calling a global function with example usage: _get_schedule_rules_for_x86(intrin) and returns: list