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README.md
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The data, excluding the projects and logs, were then further processed into a collection of JSON files, distributed alongside this paper and described below.
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- **Repository:** [fastmachinelearning/wa-hls4ml-paper](https://github.com/fastmachinelearning/wa-hls4ml-paper)
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- **Paper [
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## Citation
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View the paper [
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**BibTeX:**
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```bibtex
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```
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## Dataset Card Authors
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The data, excluding the projects and logs, were then further processed into a collection of JSON files, distributed alongside this paper and described below.
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- **Repository:** [fastmachinelearning/wa-hls4ml-paper](https://github.com/fastmachinelearning/wa-hls4ml-paper)
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- **Paper:** View the paper on [ACM](https://dl.acm.org/doi/10.1145/3787490) or [arXiv](https://arxiv.org/abs/2511.05615)!
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---
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## Citation
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View the paper on [ACM](https://dl.acm.org/doi/10.1145/3787490) or [arXiv](https://arxiv.org/abs/2511.05615)!
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If you use/extend this dataset, or submit to the benchmark, please cite the paper:
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**BibTeX:**
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```bibtex
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@article{10.1145/3787490,
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author = {Hawks, Benjamin and Weitz, Jason and Demler, Dmitri and Tame-Narvaez, Karla and Plotnikov, Dennis and Rahimifar, Mohammad Mehdi and Rahali, Hamza Ezzaoui and Therrien, Audrey C. and Sproule, Donovan and Khoda, Elham E. and Smith, Keegan A. and Marroquin, Russell and Di Guglielmo, Giuseppe and Tran, Nhan and Duarte, Javier and Loncar, Vladimir},
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title = {wa-hls4ml: A Benchmark and Surrogate Models for hls4ml Resource and Latency Estimation},
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year = {2026},
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issue_date = {June 2026},
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publisher = {Association for Computing Machinery},
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address = {New York, NY, USA},
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volume = {19},
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number = {2},
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issn = {1936-7406},
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url = {https://doi.org/10.1145/3787490},
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doi = {10.1145/3787490},
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abstract = {As machine learning (ML) is increasingly implemented in hardware to address real-time challenges in scientific applications, the development of advanced toolchains has significantly reduced the time required to iterate on various designs. These advancements have solved major obstacles, but also exposed new challenges. For example, processes that were not previously considered bottlenecks, such as hardware synthesis, are becoming limiting factors in the rapid iteration of designs. To mitigate these emerging constraints, multiple efforts have been undertaken to develop an ML-based surrogate model that estimates resource usage of ML accelerator architectures. We introduce wa-hls4ml, a benchmark for ML accelerator resource and latency estimation, and its corresponding initial dataset of over 680,000 fully connected and convolutional neural networks, all synthesized using hls4ml and targeting Xilinx FPGAs. The benchmark evaluates the performance of resource and latency predictors against several common ML model architectures, primarily originating from scientific domains, as exemplar models, and the average performance across a subset of the dataset. Additionally, we introduce GNN- and transformer-based surrogate models that predict latency and resources for ML accelerators. We present the architecture and performance of the models and find that the models generally predict latency and resources for the 75th percentile within several percent of the synthesized resources on the synthetic test dataset.},
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journal = {ACM Trans. Reconfigurable Technol. Syst.},
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month = may,
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articleno = {20},
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numpages = {29},
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keywords = {surrogate model, FPGA, hls4ml, resource, latency, regression, machine learning, artificial intelligence, High-level synthesis, benchmark, edge computing, graph neural network, open source}
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}
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```
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## Dataset Card Authors
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